1. Field of the Invention
The present invention relates to a non-volatile semiconductor memory device, and more particularly, to a non-volatile semiconductor memory device having an erasing gate.
2. Description of the Related Art
There is known a non-volatile semiconductor memory device having a floating gate as a non-volatile semiconductor memory device capable of retaining storage data even if a power source is turned off. In such a non-volatile semiconductor memory device described above, programming and erasing of the storage data may be performed through accumulation and release of an electric field with respect to the floating gate.
Further, as one kind of the non-volatile semiconductor memory devices having a floating gate, various split-gate type non-volatile semiconductor memory devices are proposed. FIG. 46 illustrates an example of a prior art split-gate type non-volatile semiconductor memory device.
As illustrated in FIG. 46, a source diffusion region 51 and a drain diffusion region 52 are formed on a surface layer of a substrate 50. Further, a floating gate 54 and a control gate 55 are formed on the substrate 50 via a gate insulating film 53. The control gate 55 is further electrically insulated with the floating gate 54 via a tunnel insulating film 56. A portion which opposes to the control gate 55 of the floating gate 54 has a pointed shape at an end thereof (tip section).
In a split-gate type non-volatile semiconductor memory device as described in FIG. 46, programming operation and reading operation is performed by applying a given voltage to the control gate 55, the source diffusion region 51, and the drain diffusion region 52. Besides, an erasing operation is carried out by applying a high voltage of about 12 V to the control gate 55 to draw out electrons injected to the floating gate 54 by a Fowler-Nordheim (FN) tunnel method toward the control gate 55 through the tunnel insulating film 56. Then, an intense electric field is generated in particular around the tip section due to its shape, and the electrons mainly move from the tip section to the control gate 55.
Thus, in the split-gate type non-volatile semiconductor memory device of FIG. 46, it is found that the control gate 55 also plays a role of an erasing gate. However, at the time of the erasing operation, it is necessary to apply a high voltage (about 12 V) to the control gate 55. However, for that purpose, a film thickness of the gate insulating film 53 could not be set to a given film thickness or thinner to secure a withstand voltage of the gate insulating film 53 below the control gate 55. Specifically, a current at the time of reading operation (memory cell current) could not be set as large, thereby being a factor that prevents a memory from achieving a high-speed operation, fineness, and a low voltage operation.
To solve such a problem described above, there is proposed, in addition to the above-mentioned structure, a split-gate type non-volatile semiconductor memory device further including an erasing gate (see, JP 2001-230330 A, JP 2000-286348 A, and JP 2001-085543 A). Provision of the erasing gate allows a role of the erasing gate, which is born by the control gate to be separated. As a result, there may be realized a structure with which the thickness of a gate insulating film may be further reduced.
FIG. 47 illustrates a cross sectional view illustrating a split-gate type non-volatile semiconductor memory device having the erasing gate described in JP 2001-230330 A. As illustrated in FIG. 47, a source region 61 and a drain region 62 are formed on the surface layer of the semiconductor substrate 60. Further, a floating gate 64 and a control gate 65 are formed on the semiconductor substrate 60 via a gate oxide film 63. A film thickness of the gate oxide film 63 formed below the control gate 65 is thinner than the film thickness of the gate oxide film 63 formed below the floating gate 64.
An erasing gate 68 is formed directly above the floating gate 64 via a selective oxide film 66 and a tunnel oxide film 67. An oxide film 69 is formed directly above the erasing gate 68. A sidewall oxide film 70 is formed so as to cover a sidewall of a lamination structure including the floating gate 64, the selective oxide film 66, the tunnel oxide film 67, the erasing gate 6 and the oxide film 69 above the erasing gate 68. Owing to a sidewall oxide film 70, the floating gate 64 and the erasing gate 68 are electrically isolated from the control gate 65. Further, a sidewall oxide film 71 is formed so as to cover the sidewall oxide film 70 and the control gate 65 on the source region 61 side.
Note that, the floating gate 64 is subjected to selective etching so as to form a recess at a center portion of an upper surface in a cross sectional direction which is perpendicular to a cross sectional direction of FIG. 47. With this processing, respective corner portions of both edges of the upper surface of the floating gate 64 have a pointed shape.
Thus, the non-volatile semiconductor memory device described in JP 2001-230330 A includes the floating gate 64 having a pointed shape at the upper surface thereof, the erasing gate 68 formed directly above the floating gate 64, the control gate 65 formed on a sidewall of the floating gate 64 and the erasing gate 68, and the gate oxide film 63 in which the film thickness is different between an area below the floating gate 64 and an area below the control gate 65.
Next, description is made of respective programming, reading, and erasing operations of the non-volatile semiconductor memory device described in JP 2001-230330 A. In the programming operation, voltages of 1 V, 10 V, 9 V, and 0 V are applied to the control gate 65, the erasing gate 68, the source region 61, and the drain region 62, respectively. A high voltage is applied to the erasing gate 68 and the source region 61, and hence a potential of the floating gate 64 is raised by a coupling capacitance between the source diffusion region 61 and the floating gate 64, and by a coupling capacitance between the erasing gate 68 and the floating gate 64. Hot electrons generated in the vicinity of the channel region below the region in which the floating gate 64 and the control gate 65 are arranged side by side are injected to the floating gate 64 beyond an energy barrier from a surface of the semiconductor substrate 60 to the insulating film, to thereby carry out data programming. At this time, in addition to the potential of the source region 61, the potential of the erasing gate 68 is added thereto, and hence the potential of the floating gate 64 may be efficiently increased.
In the reading out operation, voltages of 2 V, 0 V, 0 V, and 1 V are applied to the control gate 65, the erasing gate 68, the source region 61, and the drain region 62, respectively 62. At this time, in the case where an electric field (electron) has been injected to the floating gate 64, the potential of the floating gate 64 becomes lower, and hence a channel is not formed below the floating gate 64, and the current does not flow. On the other hand, in the case where an electric field (electron) has not been injected to the floating gate 64, the potential of the floating gate 64 becomes higher, and hence the channel is formed below the floating gate 64, and the memory cell current flows. Further, the film thickness of the gate oxide film 63 in an area below the control gate 65 is formed to be thin, and hence even if the voltage to be applied to the control gate 65 is set to be low, the same current may be obtained.
In the erasing operation, voltages of 0 V, 10 V, 0 V, and 0 V are applied to the control gate 65, the erasing gate 68, the source region 61, and the drain region 62, respectively. With this, the electrons injected into the floating gate 64 are released via the pointed shape on the upper surface of the floating gate 64 by means of FN tunnel to the erasing gate 68 while penetrating the tunnel oxide film 67. Further, the gate oxide film 63 and the tunnel oxide film 67 at the region below the control gate 65 may be independently formed, the film thickness of the tunnel oxide film 67 suited to the erasing operation may individually be set. As a result, the further low voltage operation is achieved.
Subsequently, description is made of a method of manufacturing a split-gate type non-volatile semiconductor memory device having the erasing gate as illustrated in FIG. 47, with reference to FIG. 48 to FIG. 51. Formed on the semiconductor substrate 60 is a lamination of the gate oxide film 63, the poly silicon film for the floating gate, the selective oxide film 66, the tunnel oxide film 67, the poly silicon film for the erasing gate, and the oxide film 69. As illustrated in FIG. 48A, a patterned resist film (not shown) is applied onto the oxide film 69, and the oxide film 69, a polysilicon film for the erasing gate, the tunnel oxide film 67, the selective oxide film 66 and the poly silicon film for the floating gate are selectively removed using the resist film. As a result, the floating gate 64 and the erasing gate 68 are formed. At this time, a part of the exposed gate oxide film 63 is etched, and the thickness of the gate oxide film 63 at an area below a control gate 65, which is formed by the subsequent process, becomes thinner.
Besides, FIG. 48B illustrates a cross section in a direction orthogonal to FIG. 48A. The respective memory cells are electrically isolated by the element isolation film (LOCOS) 72. Further, on an upper surface of the floating gate 64, the selective oxide film is formed so that a recess is formed at a center portion thereof, and each of the corner portions at both ends of the floating gate 64 has a pointed shape.
Next, as illustrated in FIG. 49, the sidewall oxide film 70 is formed so as to cover the sides of oxide film 69, the erasing gate 68, the tunnel oxide film 67, the selective oxide film 66, and the floating gate 64 on the erasing gate 68.
Next, a polysilicon film is formed on an entire surface of the semiconductor substrate 60, and anisotropic etching is performed to form sidewall conductive films so as to cover the sidewall oxide film 70. After that, as illustrated in FIG. 50, one of the sidewall conductive films is removed using the resist film 73 as a mask. As a result, the remaining sidewall conductive film becomes the control gate 65.
Next, as illustrated in FIG. 51, ion injection is performed using the resist film 73 as the mask to form the source region 61. After that, the resist film 73 is removed, and the sidewall oxide film 71 is formed on the side surfaces of the sidewall oxide film 70 and the control gate 65 on the source region 61 side. Then, a resist film covering the source region 61 is formed, and the ion injection is performed to form the drain region 62. Thus, the split-gate type non-volatile semiconductor memory device having the erasing gate shown in FIG. 47 is completed.
Besides, JP 2000-286348 A describes a split-gate type non-volatile semiconductor memory device having an erasing gate which is different from one disclosed in JP 2001-230330 A. Description is made of a device structure of the non-volatile semiconductor memory device described in JP 2000-286348 A with reference to FIG. 52 and FIG. 53.
As illustrated in FIG. 52, a source region 81 and a drain region 82 are formed on a surface layer of a silicon substrate 80. Further, a floating gate 84, a control gate 85 and an erasing gate 86 are formed in parallel via a gate oxide film 83 on the silicon substrate 80. The floating gate 84, the control gate 85, and the erasing gate 86 each are electrically isolated by the silicon oxide films 87 and 88. Note that, the surface layers of the drain region 82, the control gate 85, and the erasing gate 86 are subjected to silicidation (89, 90, and 91 each represent titanium silicide film), and hence a lower resistance is achieved.
The erasing gate 86 of JP 2000-286348 A is not positioned directly above the floating gate 84 different from that of JP 2001-230330 A, and is positioned directly above the source region 81. For that reason, as illustrated in FIG. 53, to realize a contact with the source region 81, the erasing gate 86 is divided so that a part of the lower source region 81 is exposed. Further, the erasing gate 86 and the source region 81 are connected to each other via a transistor 92. At the time of data programming, the transistor 92 is turned ON, and the erasing gate 86 and the source region 81 are in a conductive state. On the other hand, at the time of data erasing the transistor 92 is turned OFF, and the erasing gate 86 and the source region 81 are in a non-conductive state.
Besides, in JP 2001-085543 A, there is described a split-gate type non-volatile semiconductor memory device having an erasing gate which is different from that shown in JP 2001-230330 A and JP 2000-286348 A. The device structure of the non-volatile semiconductor memory device described in JP 2001-085543 A is described with reference to FIG. 54.
As illustrated in FIG. 54, a source region 101 and a drain region 102 are formed on the surface layer of the silicon substrate 100. Further, a floating gate 106 and a control gate 105 are formed side by side via a floating gate insulating film 104 and a control gate insulating film 103 formed on the silicon substrate 100. An erasing gate 107 is formed via an erasing gate the insulating film 108 and a silicon oxide film 109 so as to cover the floating gate 106, the control gate 105, and a source wiring 110.
In FIG. 54, three memory cells are illustrated (region sectioned by a dotted line constitutes one memory cell). The adjacent memory cells each share the source region 101 (the source wiring 110) and the drain region 102, and the source region 101 and the drain region 102 are formed symmetrically so that respective electrodes are arranged inversely. Further, the erasing gate 107 and the source wiring 110 are connected to the memory cells, which are adjacent to a perpendicular direction with respect to a cross-sectional direction of FIG. 54.
Thus, in JP 2000-286348 A and JP 2001-085543, the structure having the erasing gate positioned directly above the floating gate as described in JP 2001-230330 A is not employed, and the structure having the erasing gate positioned on an upper layer of the source region (the source wiring) or the control gate is employed. In the structure having the erasing gate directly above the floating gate, the conductive film for the floating gate and the conductive film for the erasing gate are simultaneously etched so that the floating gate and the erasing gate are formed in pair. Specifically, in JP 2001-230330 A, different from the structures of JP 2000-286348 A and JP 2001-085543 A, one erasing gate is formed per one floating gate, thereby being capable of making a unit for erasing to be small. Besides, a mask is necessary to be used when dividing the erasing gate in JP 2000-286348 A, and when forming the erasing gate in JP 2001-085543 A, manufacturing steps thereof may be complicate and intricate.
In recent years, in a microcontroller built in flash memory, achievements of higher operation speed, lower power consumption, and higher function are advancing more and more. For that reason, with respect to a built-in flash memory, too, the achievements of the higher operation speed, operation in a lower voltage, and high definition are coming to be required.
For the achievement of the high definition, it becomes important to form the respective members in a self-alignment method as much as possible, and to eliminate margins for displacement of the mask, thereby reducing the sizes of the memory cells. Further, the formation in a self-alignment method may simplify the manufacturing steps.
The present inventor has recognized that, in JP 2001-230330 A, the plug is not formed on the source. For that reason, after formation of an interlayer insulating film, a contact hole for an establishment of a contact with the source must be formed, thereby being necessary to use the mask thereat. Specifically, in order to secure the sufficient margins for the displacement of the mask, the fining of the memory cells may be prevented from being achieved. Further, in JP 2001-230330 A, the mask is used at the formation of the source and the drain. In addition, at the formation of the contact hole in the source, the mask must be used. Specifically, it results in promoting the complication and intrication of the manufacturing steps.